Re: [PATCH v5 13/60] target/riscv: vector single-width bit shift instructions

On 3/12/20 7:58 AM, LIU Zhiwei wrote: > +#define GEN_OPIVX_GVEC_SHIFT_TRANS(NAME, GVSUF) > \ > +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) > \ > +{ > \ > +

[PATCH v5 13/60] target/riscv: vector single-width bit shift instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvv.inc.c | 44 + target/riscv/vector_helper.c| 82 + 4 files changed, 160 insertion