Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

2020-09-10 Thread Alistair Francis
On Wed, Sep 9, 2020 at 12:51 PM Palmer Dabbelt wrote: > > On Wed, 09 Sep 2020 12:00:07 PDT (-0700), Peter Maydell wrote: > > On Wed, 9 Sep 2020 at 19:00, Alistair Francis wrote: > >> > >> On Tue, Sep 8, 2020 at 7:52 AM Peter Maydell > >> wrote: > >> > ...shouldn't the riscv64-softmmu config hav

Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

2020-09-09 Thread Palmer Dabbelt
On Wed, 09 Sep 2020 12:00:07 PDT (-0700), Peter Maydell wrote: On Wed, 9 Sep 2020 at 19:00, Alistair Francis wrote: On Tue, Sep 8, 2020 at 7:52 AM Peter Maydell wrote: > ...shouldn't the riscv64-softmmu config have CONFIG_OPENTITAN too? > The usual principle is that the 64-bit executable can

Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

2020-09-09 Thread Peter Maydell
On Wed, 9 Sep 2020 at 19:00, Alistair Francis wrote: > > On Tue, Sep 8, 2020 at 7:52 AM Peter Maydell wrote: > > ...shouldn't the riscv64-softmmu config have CONFIG_OPENTITAN too? > > The usual principle is that the 64-bit executable can run the > > 32-bit boards too. > > I didn't know that was t

Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

2020-09-09 Thread Alistair Francis
On Tue, Sep 8, 2020 at 7:52 AM Peter Maydell wrote: > > On Thu, 28 May 2020 at 23:31, Alistair Francis > wrote: > > > > This adds a barebone OpenTitan machine to QEMU. > > > > Signed-off-by: Alistair Francis > > Reviewed-by: Bin Meng > > --- > > default-configs/riscv32-softmmu.mak | 1 + > >

Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

2020-09-08 Thread Peter Maydell
On Thu, 28 May 2020 at 23:31, Alistair Francis wrote: > > This adds a barebone OpenTitan machine to QEMU. > > Signed-off-by: Alistair Francis > Reviewed-by: Bin Meng > --- > default-configs/riscv32-softmmu.mak | 1 + > default-configs/riscv64-softmmu.mak | 11 +- Just noticed this, but: > d

Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

2020-06-09 Thread Alistair Francis
On Tue, Jun 9, 2020 at 7:21 AM Philippe Mathieu-Daudé wrote: > > On 6/9/20 3:48 PM, Damien Hedde wrote: > > > > Hi Alistair, > > > > On 5/29/20 12:14 AM, Alistair Francis wrote: > >> This adds a barebone OpenTitan machine to QEMU. > >> > >> Signed-off-by: Alistair Francis > >> Reviewed-by: Bin Me

Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

2020-06-09 Thread Philippe Mathieu-Daudé
On 6/9/20 3:48 PM, Damien Hedde wrote: > > Hi Alistair, > > On 5/29/20 12:14 AM, Alistair Francis wrote: >> This adds a barebone OpenTitan machine to QEMU. >> >> Signed-off-by: Alistair Francis >> Reviewed-by: Bin Meng >> --- > >> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/op

Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

2020-06-09 Thread Damien Hedde
Hi Alistair, On 5/29/20 12:14 AM, Alistair Francis wrote: > This adds a barebone OpenTitan machine to QEMU. > > Signed-off-by: Alistair Francis > Reviewed-by: Bin Meng > --- > diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h > new file mode 100644 > index 00..

[PATCH v5 06/11] riscv: Initial commit of OpenTitan machine

2020-05-28 Thread Alistair Francis
This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- default-configs/riscv32-softmmu.mak | 1 + default-configs/riscv64-softmmu.mak | 11 +- include/hw/riscv/opentitan.h| 68 ++ hw/riscv/opentitan.c| 184 ++