Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions

2020-03-13 Thread LIU Zhiwei
On 2020/3/14 9:26, Richard Henderson wrote: On 3/13/20 2:32 PM, LIU Zhiwei wrote: +/* check functions */ +static bool vext_check_isa_ill(DisasContext *s, target_ulong isa) +{ +    return !s->vill && ((s->misa & isa) == isa); +} I don't think we need a new function to check ISA. I don't thin

Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions

2020-03-13 Thread Richard Henderson
On 3/12/20 7:58 AM, LIU Zhiwei wrote: > Vector strided operations access the first memory element at the base address, > and then access subsequent elements at address increments given by the byte > offset contained in the x register specified by rs2. > > Vector unit-stride operations access eleme

Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions

2020-03-13 Thread Richard Henderson
On 3/13/20 2:32 PM, LIU Zhiwei wrote: >>> +/* check functions */ >>> +static bool vext_check_isa_ill(DisasContext *s, target_ulong isa) >>> +{ >>> +    return !s->vill && ((s->misa & isa) == isa); >>> +} >> I don't think we need a new function to check ISA. > I don't think so. > > Although there i

Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions

2020-03-13 Thread Alistair Francis
On Fri, Mar 13, 2020 at 3:17 PM LIU Zhiwei wrote: > > > > On 2020/3/14 6:05, Alistair Francis wrote: > > On Fri, Mar 13, 2020 at 2:32 PM LIU Zhiwei wrote: > >> > >> > >> On 2020/3/14 4:38, Alistair Francis wrote: > >>> On Thu, Mar 12, 2020 at 8:09 AM LIU Zhiwei wrote: > Vector strided opera

Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions

2020-03-13 Thread LIU Zhiwei
On 2020/3/14 6:05, Alistair Francis wrote: On Fri, Mar 13, 2020 at 2:32 PM LIU Zhiwei wrote: On 2020/3/14 4:38, Alistair Francis wrote: On Thu, Mar 12, 2020 at 8:09 AM LIU Zhiwei wrote: Vector strided operations access the first memory element at the base address, and then access subseq

Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions

2020-03-13 Thread Alistair Francis
On Fri, Mar 13, 2020 at 2:32 PM LIU Zhiwei wrote: > > > > On 2020/3/14 4:38, Alistair Francis wrote: > > On Thu, Mar 12, 2020 at 8:09 AM LIU Zhiwei wrote: > >> Vector strided operations access the first memory element at the base > >> address, > >> and then access subsequent elements at address

Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions

2020-03-13 Thread LIU Zhiwei
On 2020/3/14 4:38, Alistair Francis wrote: On Thu, Mar 12, 2020 at 8:09 AM LIU Zhiwei wrote: Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified

Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions

2020-03-13 Thread Alistair Francis
On Thu, Mar 12, 2020 at 8:09 AM LIU Zhiwei wrote: > > Vector strided operations access the first memory element at the base address, > and then access subsequent elements at address increments given by the byte > offset contained in the x register specified by rs2. > > Vector unit-stride operation

[PATCH v5 05/60] target/riscv: add vector stride load and store instructions

2020-03-12 Thread LIU Zhiwei
Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from