On 7/16/20 1:04 AM, Havard Skinnemoen wrote:
> On Wed, Jul 15, 2020 at 12:25 AM Philippe Mathieu-Daudé
> wrote:
>> On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
>>> The NPCM730 and NPCM750 SoCs have three timer modules each holding five
>>> timers and some shared registers (e.g. interrupt status).
On Wed, Jul 15, 2020 at 12:25 AM Philippe Mathieu-Daudé wrote:
>
> On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
> > The NPCM730 and NPCM750 SoCs have three timer modules each holding five
> > timers and some shared registers (e.g. interrupt status).
> >
> > Each timer runs at 25 MHz divided by a pr
On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
> The NPCM730 and NPCM750 SoCs have three timer modules each holding five
> timers and some shared registers (e.g. interrupt status).
>
> Each timer runs at 25 MHz divided by a prescaler, and counts down from a
> configurable initial value to zero. When
The NPCM730 and NPCM750 SoCs have three timer modules each holding five
timers and some shared registers (e.g. interrupt status).
Each timer runs at 25 MHz divided by a prescaler, and counts down from a
configurable initial value to zero. When zero is reached, the interrupt
flag for the timer is s
