Re: [PATCH v4 4/9] target/riscv: Implement Ssdbltrp exception handling

2024-10-20 Thread Alistair Francis
On Fri, Oct 18, 2024 at 12:54 AM Clément Léger wrote: > > When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode > while SSTATUS.SDT isn't cleared, generate a double trap exception to > M-mode. > > Signed-off-by: Clément Léger Reviewed-by: Alistair Francis Alistair > --- > t

[PATCH v4 4/9] target/riscv: Implement Ssdbltrp exception handling

2024-10-17 Thread Clément Léger
When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode while SSTATUS.SDT isn't cleared, generate a double trap exception to M-mode. Signed-off-by: Clément Léger --- target/riscv/cpu.c| 2 +- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 42 ++