Will do, thanks!
Dao
On Wed, Jul 20, 2022 at 10:31 PM Alistair Francis wrote:
>
> On Tue, Jul 19, 2022 at 4:02 AM Dao Lu wrote:
> >
> > ping
>
> Sorry for the delay.
>
> Do you mind rebasing this on
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next and
> sending a v5
>
> Alistair
>
On Tue, Jul 19, 2022 at 4:02 AM Dao Lu wrote:
>
> ping
Sorry for the delay.
Do you mind rebasing this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next and
sending a v5
Alistair
>
> On Tue, Jul 5, 2022 at 10:49 AM Dao Lu wrote:
> >
> > Added support for RISC-V PAUSE instruction f
On Wed, Jul 6, 2022 at 3:50 AM Dao Lu wrote:
>
> Added support for RISC-V PAUSE instruction from Zihintpause extension,
> enabled by default.
>
> Tested-by: Heiko Stuebner
> Signed-off-by: Dao Lu
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 2 ++
ping
On Tue, Jul 5, 2022 at 10:49 AM Dao Lu wrote:
>
> Added support for RISC-V PAUSE instruction from Zihintpause extension,
> enabled by default.
>
> Tested-by: Heiko Stuebner
> Signed-off-by: Dao Lu
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h
Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.
Tested-by: Heiko Stuebner
Signed-off-by: Dao Lu
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++-
t
