On Sat, Jul 6, 2024 at 7:26 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> Would it make it easier for review if we squash patch 3:
>
> [PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation
>
> and patch 8:
>
> [PATCH v4 09/14] hw/riscv/riscv-iommu: add s-stage and g-stage support
>
> In the s
Hi,
Would it make it easier for review if we squash patch 3:
[PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation
and patch 8:
[PATCH v4 09/14] hw/riscv/riscv-iommu: add s-stage and g-stage support
In the same patch?
I'm asking because I've been noticing since the first versions that s
Hi,
This new version contains changes based on suggestions made during the
v3 review [1]. Most notable changes:
- read/write locks were added in both ctx_lock and iot_lock. This code
was picked from Tomasz branch;
- a new riscv_iommu_validate_process_ctx() helper was added to make
process-con
