[PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant

Re: [PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

On Tue, Jun 4, 2024 at 7:15 PM Yu-Ming Chang via wrote: Something is strange with your `From` email address. This seems to be a common problem with the Andes emails, do you mind fixing this? Alistair > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regar

Re: [PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

On Tue, Jun 4, 2024 at 7:15 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a register > holding a zero value other than x0, the instruction will still attempt to > wri

Re: [PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

On Tue, Jun 4, 2024 at 7:15 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a register > holding a zero value other than x0, the instruction will still attempt to > wri

[PATCH v4] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant