Re: [PATCH v3 4/4] RISC-V: add vector extension configure instruction

2020-01-06 Thread LIU Zhiwei
Hi Richard, Thanks for the comments of the part 1.  It's really very helpful. I accept most of the comments. On 2020/1/4 7:41, Richard Henderson wrote: On 1/3/20 2:33 PM, LIU Zhiwei wrote: vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure i

Re: [PATCH v3 4/4] RISC-V: add vector extension configure instruction

2020-01-03 Thread Richard Henderson
On 1/3/20 2:33 PM, LIU Zhiwei wrote: > vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags > should update after configure instructions. The (ill, lmul, sew ) of vtype > and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. > > Signed-off-by: LIU Zhiwei

[PATCH v3 4/4] RISC-V: add vector extension configure instruction

2020-01-02 Thread LIU Zhiwei
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei --- target/riscv/Makefile.objs |