Re: [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU

2020-05-27 Thread Alistair Francis
On Tue, May 26, 2020 at 6:58 PM LIU Zhiwei wrote: > > > > On 2020/5/27 1:12, Alistair Francis wrote: > > On Fri, May 22, 2020 at 12:51 AM LIU Zhiwei wrote: > >> > >> > >> On 2020/5/20 5:31, Alistair Francis wrote: > >>> Ibex is a small and efficient, 32-bit, in-order RISC-V core with > >>> a 2-st

Re: [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU

2020-05-26 Thread LIU Zhiwei
On 2020/5/27 1:12, Alistair Francis wrote: On Fri, May 22, 2020 at 12:51 AM LIU Zhiwei wrote: On 2020/5/20 5:31, Alistair Francis wrote: Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture. For more

Re: [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU

2020-05-26 Thread Alistair Francis
On Fri, May 22, 2020 at 12:51 AM LIU Zhiwei wrote: > > > > On 2020/5/20 5:31, Alistair Francis wrote: > > Ibex is a small and efficient, 32-bit, in-order RISC-V core with > > a 2-stage pipeline that implements the RV32IMC instruction set > > architecture. > > > > For more details on lowRISC see he

Re: [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU

2020-05-22 Thread LIU Zhiwei
On 2020/5/20 5:31, Alistair Francis wrote: Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture. For more details on lowRISC see here: https://github.com/lowRISC/ibex Signed-off-by: Alistair Francis Revi

[PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU

2020-05-19 Thread Alistair Francis
Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture. For more details on lowRISC see here: https://github.com/lowRISC/ibex Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.h | 1