Re: [PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line

2020-01-06 Thread LIU Zhiwei
On 2020/1/7 5:48, Jim Wilson wrote: On 1/2/20 7:33 PM, LIU Zhiwei wrote: +    if (cpu->cfg.vlen > RV_VLEN_MAX) { +    error_setg(errp, +   "Vector extension VLEN must <= %d", RV_VLEN_MAX); +    return; There is no architectural maximum for

Re: [PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line

2020-01-06 Thread Jim Wilson
On 1/2/20 7:33 PM, LIU Zhiwei wrote: +if (cpu->cfg.vlen > RV_VLEN_MAX) { +error_setg(errp, + "Vector extension VLEN must <= %d", RV_VLEN_MAX); +return; There is no architectural maximum for VLEN. This is simply an implementatio

Re: [PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line

2020-01-03 Thread Richard Henderson
On 1/3/20 2:33 PM, LIU Zhiwei wrote: > +if (cpu->cfg.ext_v) { > +target_misa |= RVV; > +if (!is_power_of_2(cpu->cfg.vlen)) { > +error_setg(errp, > + "Vector extension VLEN must be power of 2"); > +return; > +

[PATCH v3 2/4] RISC-V: configure and turn on vector extension from command line

2020-01-02 Thread LIU Zhiwei
Vector extension is default on only for "any" cpu. It can be turned on by command line "-cpu rv64,vlen=128,elen=64,vext_spec=v0.7.1". vlen is the vector register length, default value is 128 bit. elen is the max operator size in bits, default value is 64 bit. vext_spec is the vector specification