That sounds reasonable to me. Will change in the next version.
Thanks,
Dao
On Sun, Jun 26, 2022 at 10:13 PM Alistair Francis wrote:
>
> On Wed, Jun 22, 2022 at 2:17 AM Dao Lu wrote:
> >
> > From what I know that's generally the way reservations are handled:
> > if the forward progress requirem
On Wed, Jun 22, 2022 at 2:17 AM Dao Lu wrote:
>
> From what I know that's generally the way reservations are handled:
> if the forward progress requirements aren't met then the implementation
> is free to break any outstanding reservations (the hardware is always
> free to do that to a degree, but
>From what I know that's generally the way reservations are handled:
if the forward progress requirements aren't met then the implementation
is free to break any outstanding reservations (the hardware is always
free to do that to a degree, but once forward progress is gone it can
always do that).
On Thu, Jun 9, 2022 at 2:42 PM Dao Lu wrote:
>
> Added support for RISC-V PAUSE instruction from Zihintpause extension,
> enabled by default.
>
> Tested-by: Heiko Stuebner
> Signed-off-by: Dao Lu
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h
Added support for RISC-V PAUSE instruction from Zihintpause extension,
enabled by default.
Tested-by: Heiko Stuebner
Signed-off-by: Dao Lu
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++-
t
Please ignore, I have missed the commit message, will resend a v3.
Sorry about that.
Dao
On Tue, Jun 7, 2022 at 8:44 PM Dao Lu wrote:
>
> Tested-by: Heiko Stuebner
> Signed-off-by: Dao Lu
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h | 1 +
Tested-by: Heiko Stuebner
Signed-off-by: Dao Lu
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 7 ++-
target/riscv/insn_trans/trans_rvi.c.inc | 18 ++
4 files changed, 27 insertio
