Re: [PATCH v3 04/10] target/riscv: Add MIPS P8700 CSRs

2025-06-25 Thread Djordje Todorovic
On 18. 6. 25. 19:59, Daniel Henrique Barboza wrote: > [You don't often get email from dbarb...@ventanamicro.com. Learn why > this is important at https://aka.ms/LearnAboutSenderIdentification ] > > CAUTION: This email originated from outside of the organization. Do > not click links or open atta

Re: [PATCH v3 04/10] target/riscv: Add MIPS P8700 CSRs

2025-06-18 Thread Daniel Henrique Barboza
On 6/18/25 9:27 AM, Djordje Todorovic wrote: Define MIPS CSRs used for P8700 CPU. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic --- target/riscv/cpu.c | 3 + target/riscv/cpu.h | 12 +++ target/riscv/meson.build | 1 + target/riscv/mips_csr.c | 219

[PATCH v3 04/10] target/riscv: Add MIPS P8700 CSRs

2025-06-18 Thread Djordje Todorovic
Define MIPS CSRs used for P8700 CPU. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic --- target/riscv/cpu.c | 3 + target/riscv/cpu.h | 12 +++ target/riscv/meson.build | 1 + target/riscv/mips_csr.c | 219 +++ 4 files changed,