Re: [PATCH v3 03/14] tcg/riscv: Add basic support for vector

On 2024/9/5 12:05, Richard Henderson wrote: On 9/4/24 07:27, LIU Zhiwei wrote: From: Swung0x48 The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each gro

Re: [PATCH v3 03/14] tcg/riscv: Add basic support for vector

On 9/4/24 07:27, LIU Zhiwei wrote: From: Swung0x48 The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each group while reserving the other register numbers w

[PATCH v3 03/14] tcg/riscv: Add basic support for vector

From: Swung0x48 The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each group while reserving the other register numbers within the group. In TCG, each VEC_IR