On 2024/9/9 23:45, Richard Henderson wrote:
On 9/9/24 00:18, LIU Zhiwei wrote:
On 2024/9/5 11:34, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
+ if (info & CPUINFO_ZVE64X) {
+ /*
+ * Get vlenb for Vector: vsetvli rd, x0, e64.
+ * VLMAX = LMUL * VLEN
On 9/9/24 00:18, LIU Zhiwei wrote:
On 2024/9/5 11:34, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
+ if (info & CPUINFO_ZVE64X) {
+ /*
+ * Get vlenb for Vector: vsetvli rd, x0, e64.
+ * VLMAX = LMUL * VLEN / SEW.
+ * The "vsetvli rd, x0, e64" me
On 2024/9/5 11:34, Richard Henderson wrote:
On 9/4/24 07:27, LIU Zhiwei wrote:
+ if (info & CPUINFO_ZVE64X) {
+ /*
+ * Get vlenb for Vector: vsetvli rd, x0, e64.
+ * VLMAX = LMUL * VLEN / SEW.
+ * The "vsetvli rd, x0, e64" means "LMUL = 1, SEW = 64, rd =
VLMA
On 9/4/24 07:27, LIU Zhiwei wrote:
+if (info & CPUINFO_ZVE64X) {
+/*
+ * Get vlenb for Vector: vsetvli rd, x0, e64.
+ * VLMAX = LMUL * VLEN / SEW.
+ * The "vsetvli rd, x0, e64" means "LMUL = 1, SEW = 64, rd = VLMAX",
+ * so "vlenb = VLMAX * 64 / 8".
+
From: TANG Tiancheng
Add support for probing RISC-V vector extension availability in
the backend. This information will be used when deciding whether
to use vector instructions in code generation.
While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X,
we use RISCV_HWPROBE_IMA_V instead.
S
