Re: [PATCH v3 02/13] hw/riscv: add riscv-iommu-bits.h

On 5/28/24 3:41 AM, Eric Cheng wrote: On 5/24/2024 1:39 AM, Daniel Henrique Barboza wrote: ... +/* 5.4 Features control register (32bits) */ +#define RISCV_IOMMU_REG_FCTL    0x0008 Looks like doesn't support RISCV_IOMMU_FCTL_BE? If so, need to implement it as read-only? along with o

Re: [PATCH v3 02/13] hw/riscv: add riscv-iommu-bits.h

On 5/24/2024 1:39 AM, Daniel Henrique Barboza wrote: ... +/* 5.4 Features control register (32bits) */ +#define RISCV_IOMMU_REG_FCTL0x0008 Looks like doesn't support RISCV_IOMMU_FCTL_BE? If so, need to implement it as read-only? along with other 2 bits. IIUC, diff --git a/hw/riscv

[PATCH v3 02/13] hw/riscv: add riscv-iommu-bits.h

From: Tomasz Jeznach This header will be used by the RISC-V IOMMU emulation to be added in the next patch. Due to its size it's being sent in separate for an easier review. One thing to notice is that this header can be replaced by the future Linux RISC-V IOMMU driver header, which would become