On Tue, Nov 5, 2024 at 3:58 PM Richard Henderson
wrote:
>
> On 11/4/24 21:51, Rajnesh Kanwal wrote:
> > target/riscv/cpu.c | 26 ++-
> > target/riscv/cpu.h | 13 ++
> > target/riscv/cpu_bits.h| 94
> >
On 11/4/24 21:51, Rajnesh Kanwal wrote:
target/riscv/cpu.c | 26 ++-
target/riscv/cpu.h | 13 ++
target/riscv/cpu_bits.h| 94
target/riscv/cpu_cfg.h | 2 +
target/riscv/cpu_
This series enables Control Transfer Records extension support on riscv
platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and this series is based on v1.0_rc6 [0]
CTR extension depends on both the implementation of S-mode and Sscsrind
extension v
