Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

2024-06-03 Thread Alistair Francis
om; > alistair.fran...@wdc.com; bin.m...@windriver.com; liwei1...@gmail.com; > dbarb...@ventanamicro.com; zhiwei_...@linux.alibaba.com > Subject: Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC > writes a read-only CSR > > [EXTERNAL MAIL] > > On Wed, Apr 3, 202

RE: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

2024-06-02 Thread 張育銘
ba.com Subject: Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR [EXTERNAL MAIL] On Wed, Apr 3, 2024 at 5:10 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fi

Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

2024-06-02 Thread Alistair Francis
On Wed, Apr 3, 2024 at 5:10 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a register > holding a zero value other than x0, the instruction will still attempt to > wri

Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

2024-04-28 Thread Alistair Francis
On Wed, Apr 3, 2024 at 5:10 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a register > holding a zero value other than x0, the instruction will still attempt to > wri

Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

2024-04-28 Thread Alistair Francis
On Wed, Apr 3, 2024 at 5:10 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a register > holding a zero value other than x0, the instruction will still attempt to > wri

[PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

2024-04-03 Thread Yu-Ming Chang via
Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant

[PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

2024-03-12 Thread Yu-Ming Chang via
Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant