On Mon, Oct 25, 2021 at 7:48 PM Jose Martins wrote:
>
> > From your last response I thought you sent a different series that
> > replaces this patch. If that's not the case do you mind sending this
> > patch again?
>
> I already sent the patch series here:
> https://lists.gnu.org/archive/html/qemu
> From your last response I thought you sent a different series that
> replaces this patch. If that's not the case do you mind sending this
> patch again?
I already sent the patch series here:
https://lists.gnu.org/archive/html/qemu-devel/2021-06/msg00553.html. I
got confused, I should have raised
On Mon, Oct 18, 2021 at 6:30 AM Jose Martins wrote:
>
> Hello Zhiwei and Alistair,
>
> I noticed this patch did not make it upstream, contrarily to a couple
> other patches I submitted around the same time. Is there something
> else needed from my side to push this forward?
>From your last respon
Hello Zhiwei and Alistair,
I noticed this patch did not make it upstream, contrarily to a couple
other patches I submitted around the same time. Is there something
else needed from my side to push this forward?
Best,
José
On Wed, 2 Jun 2021 at 20:14, Jose Martins wrote:
>
> Hello Zhiwei and Ali
Hello Zhiwei and Alistair,
I went for a middle-ground solution. I divided the patch into two: one
fixes the vs interrupt forwarding to the hypervisor, the other removes
the unnecessary force exception stuff. I just submitted the patch
series. I hope it's ok with you.
José
On Fri, 28 May 2021 at
On 5/28/21 6:34 AM, Alistair Francis wrote:
On Sun, May 23, 2021 at 1:45 AM Jose Martins wrote:
VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when
not delegated in hideleg (which was not being taken into account). This
was mainly because hs level sie was not always consider
On Sun, May 23, 2021 at 1:45 AM Jose Martins wrote:
>
> VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when
> not delegated in hideleg (which was not being taken into account). This
> was mainly because hs level sie was not always considered enabled when
> it should. The spec sta
On 5/26/21 7:50 PM, Jose Martins wrote:
Hello Zhiwei, thank you for reviewing the patch.
I'll split the patch in a series as you suggest. But first can you
help me understand what the problems are with
riscv_cpu_local_irq_pending?
I think there are two errors in riscv_cpu_local_irq_pending.
Hello Zhiwei, thank you for reviewing the patch.
I'll split the patch in a series as you suggest. But first can you
help me understand what the problems are with
riscv_cpu_local_irq_pending?
> I think there are two errors in riscv_cpu_local_irq_pending.
>
> 1) VS interrupts can't be forwarded to
Hi Jose,
For one patch, the commit message is too long and complex. I recommend
to split
this patch to a patch set with 4 patches. The tremohread topic is
'target/riscv: Remove force hs exception'
1) Define the right hsie to select pending_hs_irqs.
diff --git a/target/riscv/cpu_helper.c b/t
VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when
not delegated in hideleg (which was not being taken into account). This
was mainly because hs level sie was not always considered enabled when
it should. The spec states that "Interrupts for higher-privilege modes,
y>x, are alway
11 matches
Mail list logo
