Re: [PATCH v3] target/riscv: Fix shift count overflow

2024-03-06 Thread Alistair Francis
On Mon, Feb 26, 2024 at 3:42 AM demin.han wrote: > > The result of (8 - 3 - vlmul) is negative when vlmul >= 6, > and results in wrong vill. > > Signed-off-by: demin.han Thanks! Applied to riscv-to-apply.next Alistair > --- > Changes in v2: > - Add vlen var > > Changes in v3: > - Fix commit m

Re: [PATCH v3] target/riscv: Fix shift count overflow

2024-03-06 Thread Daniel Henrique Barboza
Hi Alistair, Please don't forget to queue this up. Thanks, Daniel On 2/26/24 06:31, Daniel Henrique Barboza wrote: On 2/25/24 14:41, demin.han wrote: The result of (8 - 3 - vlmul) is negative when vlmul >= 6, and results in wrong vill. Signed-off-by: demin.han --- Reviewed-by: Daniel

Re: [PATCH v3] target/riscv: Fix shift count overflow

2024-02-26 Thread Daniel Henrique Barboza
On 2/25/24 14:41, demin.han wrote: The result of (8 - 3 - vlmul) is negative when vlmul >= 6, and results in wrong vill. Signed-off-by: demin.han --- Reviewed-by: Daniel Henrique Barboza Changes in v2: - Add vlen var Changes in v3: - Fix commit msg typo target/riscv/vector_helper.c

[PATCH v3] target/riscv: Fix shift count overflow

2024-02-25 Thread demin.han
The result of (8 - 3 - vlmul) is negative when vlmul >= 6, and results in wrong vill. Signed-off-by: demin.han --- Changes in v2: - Add vlen var Changes in v3: - Fix commit msg typo target/riscv/vector_helper.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/ris