Re: [PATCH v3] hw/riscv: microchip_pfsoc: Correct DDR memory map

2020-11-01 Thread Alistair Francis
On Sun, Nov 1, 2020 at 8:51 AM Bin Meng wrote: > > Hi Alistair, > > On Mon, Nov 2, 2020 at 12:46 AM Alistair Francis wrote: > > > > On Sun, Nov 1, 2020 at 8:42 AM Bin Meng wrote: > > > > > > From: Bin Meng > > > > > > When system memory is larger than 1 GiB (high memory), PolarFire SoC > > > ma

Re: [PATCH v3] hw/riscv: microchip_pfsoc: Correct DDR memory map

2020-11-01 Thread Bin Meng
Hi Alistair, On Mon, Nov 2, 2020 at 12:46 AM Alistair Francis wrote: > > On Sun, Nov 1, 2020 at 8:42 AM Bin Meng wrote: > > > > From: Bin Meng > > > > When system memory is larger than 1 GiB (high memory), PolarFire SoC > > maps it at address 0x10__. Address 0xC000_ and above is > >

Re: [PATCH v3] hw/riscv: microchip_pfsoc: Correct DDR memory map

2020-11-01 Thread Alistair Francis
On Sun, Nov 1, 2020 at 8:42 AM Bin Meng wrote: > > From: Bin Meng > > When system memory is larger than 1 GiB (high memory), PolarFire SoC > maps it at address 0x10__. Address 0xC000_ and above is > aliased to the same 1 GiB low memory with different cache attributes. > > At present Q

[PATCH v3] hw/riscv: microchip_pfsoc: Correct DDR memory map

2020-11-01 Thread Bin Meng
From: Bin Meng When system memory is larger than 1 GiB (high memory), PolarFire SoC maps it at address 0x10__. Address 0xC000_ and above is aliased to the same 1 GiB low memory with different cache attributes. At present QEMU maps the system memory contiguously from 0x8000_. This