Re: [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations

On Thu, Apr 1, 2021 at 11:20 PM Alistair Francis wrote: > > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.h | 14 +- > target/riscv/csr.c | 643 +++-- > 2 files changed, 390 insertions(+), 267 deletions(-) > Reviewed-by: Bin Meng

Re: [PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations

On 4/1/21 8:17 AM, Alistair Francis wrote: Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 14 +- target/riscv/csr.c | 643 +++-- 2 files changed, 390 insertions(+), 267 deletions(-) Reviewed-by: Richard Henderson r~

[PATCH v2 4/5] target/riscv: Use the RISCVException enum for CSR operations

Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 14 +- target/riscv/csr.c | 643 +++-- 2 files changed, 390 insertions(+), 267 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1291ddc381..7b9b9da6b7 100644 --- a/target/risc