On 4/26/22 16:08, Atish Patra wrote:
+static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
+target_ulong val)
+{
+RISCVCPU *cpu = env_archcpu(env);
+
+if (riscv_cpu_mxl(env) == MXL_RV32) {
+uint64_t stimecmp_hi = env->stimecmp >>
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 8
target/riscv/cpu.h | 5 ++
target/riscv/cpu_b
