Re: [PATCH v2 3/6] target/ppc: Fix instruction loading endianness in alignment interrupt

On 3/27/23 18:42, Nicholas Piggin wrote: powerpc ifetch endianness depends on MSR[LE] so it has to byteswap after cpu_ldl_code(). This corrects DSISR bits in alignment interrupts when running in little endian mode. Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas --- Since v1: - Rem

Re: [PATCH v2 3/6] target/ppc: Fix instruction loading endianness in alignment interrupt

Nicholas Piggin writes: > powerpc ifetch endianness depends on MSR[LE] so it has to byteswap > after cpu_ldl_code(). This corrects DSISR bits in alignment > interrupts when running in little endian mode. > > Signed-off-by: Nicholas Piggin Reviewed-by: Fabiano Rosas

[PATCH v2 3/6] target/ppc: Fix instruction loading endianness in alignment interrupt

powerpc ifetch endianness depends on MSR[LE] so it has to byteswap after cpu_ldl_code(). This corrects DSISR bits in alignment interrupts when running in little endian mode. Signed-off-by: Nicholas Piggin --- Since v1: - Removed big endian ifdef [Fabiano review] - Acaually use need_byswap helper.