Re: [PATCH v2 2/9] target/riscv: Add cpu_set_exception_base

2025-06-18 Thread Djordje Todorovic
On 10. 6. 25. 09:43, Philippe Mathieu-Daudé wrote: > CAUTION: This email originated from outside of the organization. Do > not click links or open attachments unless you recognize the sender > and know the content is safe. > > > On 2/6/25 15:12, Djordje Todorovic wrote: >> Add a new function, so

Re: [PATCH v2 2/9] target/riscv: Add cpu_set_exception_base

2025-06-10 Thread Alistair Francis
On Mon, Jun 2, 2025 at 11:15 PM Djordje Todorovic wrote: > > Add a new function, so we can change reset vector from platforms. You can use the "resetvec" property instead, there are a range of RISC-V machines already doing this. Have a look at hw/riscv/opentitan.c or hw/riscv/sifive_u.c for examp

Re: [PATCH v2 2/9] target/riscv: Add cpu_set_exception_base

2025-06-10 Thread Philippe Mathieu-Daudé
On 2/6/25 15:12, Djordje Todorovic wrote: Add a new function, so we can change reset vector from platforms. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic --- target/riscv/cpu.h | 2 ++ target/riscv/translate.c | 8 2 files changed, 10 insertions(+) diff --git

[PATCH v2 2/9] target/riscv: Add cpu_set_exception_base

2025-06-02 Thread Djordje Todorovic
Add a new function, so we can change reset vector from platforms. Signed-off-by: Chao-ying Fu Signed-off-by: Djordje Todorovic --- target/riscv/cpu.h | 2 ++ target/riscv/translate.c | 8 2 files changed, 10 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h inde