Re: [PATCH v2 1/8] target/riscv: Add Ssdbltrp CSRs handling

On Wed, Sep 25, 2024 at 10:02 PM Clément Léger wrote: > > Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, > {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the > presence of the Ssdbltrp ISA extension. > > Signed-off-by: Clément Léger Reviewed-by: Alistair Francis

[PATCH v2 1/8] target/riscv: Add Ssdbltrp CSRs handling

Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the presence of the Ssdbltrp ISA extension. Signed-off-by: Clément Léger --- target/riscv/cpu.h| 1 + target/riscv/cpu_bits.h | 6 ++ target/riscv/cpu_cfg.