On Monday, November 30, 2020 5:54 PM, Peter Maydell wrote:
> On Mon, 30 Nov 2020 at 05:41, Wu, Wentong wrote:
> > Reviewed and tested.
>
> Thanks! Can I put that in as Reviewed-by/Tested-by lines?
Sure and my pleasure, thanks Peter!
>
> -- PMM
On 11/29/20 6:40 PM, Peter Maydell wrote:
> The Nios2 architecture supports two different interrupt controller
> options:
>
> * The IIC (Internal Interrupt Controller) is part of the CPU itself;
>it has 32 IRQ input lines and no NMI support. Interrupt status is
>queried and controlled vi
On Mon, 30 Nov 2020 at 05:41, Wu, Wentong wrote:
> Reviewed and tested.
Thanks! Can I put that in as Reviewed-by/Tested-by lines?
-- PMM
On Monday, November 30, 2020 1:40 AM, Peter Maydell wrote:
> The Nios2 architecture supports two different interrupt controller
> options:
>
> * The IIC (Internal Interrupt Controller) is part of the CPU itself;
>it has 32 IRQ input lines and no NMI support. Interrupt status is
>queried
The Nios2 architecture supports two different interrupt controller
options:
* The IIC (Internal Interrupt Controller) is part of the CPU itself;
it has 32 IRQ input lines and no NMI support. Interrupt status is
queried and controlled via the CPU's ipending and istatus
registers.
* The
