Re: [PATCH v2 1/2] target/riscv: FIX xATP_MODE validation

On Tue, Dec 12, 2023 at 9:04 PM Irina Ryapolova wrote: > > [Changes since v1] > used satp_mode.map instead of satp_mode.supported The changelog needs to go > > [Original cover] > The SATP register is an SXLEN-bit read/write WARL register. It means that CSR > fields are only defined > for a subs

Re: [PATCH v2 1/2] target/riscv: FIX xATP_MODE validation

Hi, On 12/12/23 08:03, Irina Ryapolova wrote: [Changes since v1] used satp_mode.map instead of satp_mode.supported [Original cover] The SATP register is an SXLEN-bit read/write WARL register. It means that CSR fields are only defined for a subset of bit encodings, but allow any value to be wri

[PATCH v2 1/2] target/riscv: FIX xATP_MODE validation

[Changes since v1] used satp_mode.map instead of satp_mode.supported [Original cover] The SATP register is an SXLEN-bit read/write WARL register. It means that CSR fields are only defined for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal value