On 2/8/21 11:30 AM, Peter Maydell wrote:
> On Mon, 8 Feb 2021 at 18:58, Richard Henderson
> wrote:
>>
>> On 2/8/21 10:28 AM, Peter Maydell wrote:
>>> On Mon, 8 Feb 2021 at 17:53, Peter Maydell wrote:
The AAPCS says that q4-q7 are preserved across calls.
>>>
>>> Speaking of which, doesn't tha
On Mon, 8 Feb 2021 at 18:58, Richard Henderson
wrote:
>
> On 2/8/21 10:28 AM, Peter Maydell wrote:
> > On Mon, 8 Feb 2021 at 17:53, Peter Maydell wrote:
> >> The AAPCS says that q4-q7 are preserved across calls.
> >
> > Speaking of which, doesn't that mean we also need to
> > save and restore q4-
On 2/8/21 10:28 AM, Peter Maydell wrote:
> On Mon, 8 Feb 2021 at 17:53, Peter Maydell wrote:
>> The AAPCS says that q4-q7 are preserved across calls.
>
> Speaking of which, doesn't that mean we also need to
> save and restore q4-q7 in tcg_target_qemu_prologue()
> if we might be generating neon in
On Mon, 8 Feb 2021 at 17:53, Peter Maydell wrote:
> The AAPCS says that q4-q7 are preserved across calls.
Speaking of which, doesn't that mean we also need to
save and restore q4-q7 in tcg_target_qemu_prologue()
if we might be generating neon insns? (It doesn't look like
aarch64's prologue does t
On Mon, 8 Feb 2021 at 03:48, Richard Henderson
wrote:
>
> Add registers and function stubs. The functionality
> is disabled via use_neon_instructions defined to 0.
>
> We must still include results for the mandatory opcodes in
> tcg_target_op_def, as all opcodes are checked during tcg init.
>
> S
Add registers and function stubs. The functionality
is disabled via use_neon_instructions defined to 0.
We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-con-set.h |
