Re: [PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo

2024-09-01 Thread Richard Henderson
On 8/30/24 16:15, LIU Zhiwei wrote: +extern unsigned riscv_vlen; Do you really want to store vlen and not vlenb? It seems that would simplify some of your computation in the tcg backend. @@ -49,6 +50,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #endif #if defined(__riscv

[PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo

2024-08-29 Thread LIU Zhiwei
From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. While the compiler doesn't support RISCV_HWPROBE_EXT_ZVE64X, we use RISCV_HWPROBE_IMA_V instead. S