On 10/22/24 17:23, Kevin Wolf wrote:
Am 22.10.2024 um 15:40 hat Cédric Le Goater geschrieben:
static const VMStateDescription vmstate_aspeed_smc = {
.name = "aspeed.smc",
-.version_id = 2,
+.version_id = 3,
.minimum_version_id = 2,
.fields = (const VMStateField[])
On 10/23/24 03:41, Jamin Lin wrote:
Hi Cedric,
Subject: Re: [PATCH v2 01/18] aspeed/smc: Fix write incorrect data into flash in
user mode
static const VMStateDescription vmstate_aspeed_smc = {
.name = "aspeed.smc",
-.version_id = 2,
+.vers
Hi Cedric,
> Subject: Re: [PATCH v2 01/18] aspeed/smc: Fix write incorrect data into flash
> in
> user mode
>
> >>
> >> static const VMStateDescription vmstate_aspeed_smc = {
> >> .name = "aspeed.smc",
> >> -.version_id = 2,
Am 22.10.2024 um 15:40 hat Cédric Le Goater geschrieben:
> > > static const VMStateDescription vmstate_aspeed_smc = {
> > > .name = "aspeed.smc",
> > > -.version_id = 2,
> > > +.version_id = 3,
> > > .minimum_version_id = 2,
> > > .fields = (const VMStateField[]) {
> > >
static const VMStateDescription vmstate_aspeed_smc = {
.name = "aspeed.smc",
-.version_id = 2,
+.version_id = 3,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
VMSTATE_UINT
Am 22.10.2024 um 11:40 hat Jamin Lin geschrieben:
> According to the design of ASPEED SPI controllers user mode, users write the
> data to flash, the SPI drivers set the Control Register(0x10) bit 0 and 1
> enter user mode. Then, SPI drivers send flash commands for writing data.
> Finally, SPI driv
On 10/22/24 11:40, Jamin Lin wrote:
According to the design of ASPEED SPI controllers user mode, users write the
data to flash, the SPI drivers set the Control Register(0x10) bit 0 and 1
enter user mode. Then, SPI drivers send flash commands for writing data.
Finally, SPI drivers set the Control
According to the design of ASPEED SPI controllers user mode, users write the
data to flash, the SPI drivers set the Control Register(0x10) bit 0 and 1
enter user mode. Then, SPI drivers send flash commands for writing data.
Finally, SPI drivers set the Control Register (0x10) bit 2 to stop
active c
