This series provides few cleanups and fixes for the amd iommu
Changes since v1:
- Dropped top two patches which depend on the Alejandro's changes and rebased
remaining patches on top of v10.1.0-rc0 [Phil].
- Added a patch to fix amdvi_write*() [Ethon].
- Reset event log head and tail when guest
On 7/21/25 12:33 PM, Pierrick Bouvier wrote:
This plugin generates a binary trace compatible with the excellent uftrace:
https://github.com/namhyung/uftrace
In short, it tracks all function calls performed during execution, based on
frame pointer analysis. A big advantage over "uftrace record" i
This plugin generates a binary trace compatible with the excellent uftrace:
https://github.com/namhyung/uftrace
In short, it tracks all function calls performed during execution, based on
frame pointer analysis. A big advantage over "uftrace record" is that it works
in system mode, allowing to tra
On 5/2/25 6:27 AM, Shameer Kolothum wrote:
Hi All,
Changes from v1:
https://lore.kernel.org/qemu-devel/20250415081104.71708-1-shameerali.kolothum.th...@huawei.com/
Addressed feedback on v1. Thanks to all.
1. Retained the same name as the legacy SMMUv3(arm-smmuv3) for new
device type as w
Hi All,
Changes from v1:
https://lore.kernel.org/qemu-devel/20250415081104.71708-1-shameerali.kolothum.th...@huawei.com/
Addressed feedback on v1. Thanks to all.
1. Retained the same name as the legacy SMMUv3(arm-smmuv3) for new
device type as well (instead of arm-smmuv3-dev type usage in v1).
On 2025/4/17 下午6:03, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 17/4/25 05:51, Bibo Mao wrote:
Get physical address from virtual address is important for qmp command to
dump memory content. In TCG mode, it searches TLB tables firstly and
then do page table walker. In KVM mode, there are no TL
Hi Bibo,
On 17/4/25 05:51, Bibo Mao wrote:
Get physical address from virtual address is important for qmp command to
dump memory content. In TCG mode, it searches TLB tables firstly and
then do page table walker. In KVM mode, there are no TLB tables and page
table walker is used directly.
Here
Get physical address from virtual address is important for qmp command to
dump memory content. In TCG mode, it searches TLB tables firstly and
then do page table walker. In KVM mode, there are no TLB tables and page
table walker is used directly.
Here TLB tables searching is moved to directory tcg
As defined by:
https://github.com/rfbproto/rfbproto/blob/master/rfbproto.rst#open-h-264-encoding
The noVNC HTML application recently added support for this encoding. There is
also an open pull request to add audio support to noVNC:
https://github.com/novnc/noVNC/pull/1952
With that in place, th
From: Qiang Yu
mesa/radeonsi is going to support explicit modifier with this MR:
* https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658
The side effect is some texture will become multi-plane which
breaks qemu. Because qemu currently only support single plane
texture.
For example,
To address the limitation that this option is incompatible with
remote clients, this patch series adds an option to select a
preferred codec and also enable gl=on option for clients that
are connected via the network. In other words, with this option
enabled (and the below linked Spice series merge
QEMU 9.2 already fixed the long standing limitation of failing fstat() on
unlinked files. This series does something similar for ftruncate().
The following program can be straced inside the guest with a shared fs in
passthrough mode over 9p2000.L.
int main(void)
{
struct stat st;
On Tue, Feb 25, 2025 at 10:55 AM Sebastian Huber
wrote:
>
> Booting the microchip-icicle-kit machine using the latest PolarFire SoC
> Hart Software Services (HSS) no longer works since Qemu lacks support
> for several registers (clocks, DRAM controller). Also reading from the
> SDCard does not wor
QOM properties could use similar work. Left for another day.
v2: Rebased
Markus Armbruster (6):
qdev: Delete unused qdev_prop_enum
qdev: Change qdev_prop_pci_devfn member @name from "int32" to "str"
qdev: Rename PropertyInfo member @name to @type
qdev: Change values of PropertyInfo membe
Booting the microchip-icicle-kit machine using the latest PolarFire SoC
Hart Software Services (HSS) no longer works since Qemu lacks support
for several registers (clocks, DRAM controller). Also reading from the
SDCard does not work currently.
In order to allow tests runs for real-time kernels su
This is the v2 series of the shared device assignment support.
The overview of this series:
- Patch 1-2: preparation patches. One is to export a helper to get
intersection of a MemoryRegionSection with a given range. The other is
to change the memory_region_set_ram_discard_manager() to return
CC here
Cc: Jamin Lin ; Troy Lee
; Yunlin Tang
Subject: [PATCH v2 0/6] INTC model cleanup
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.246
5942-1-jamin_...@aspeedtech.com
> Cc: Jamin Lin ; Troy Lee
> ; Yunlin Tang
> Subject: [PATCH v2 0/6] INTC model cleanup
>
> v2:
> To streamline the review process, split the following patch series into
> three parts.
>
> https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.246
&g
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_...@aspeedtech.com/
This patch series focuses on cleaning up the INTC model to
facilitate future support for the I
On Thu, 30 Jan 2025 at 11:26, Philippe Mathieu-Daudé wrote:
>
> (series fully reviewed)
>
> Hi,
>
> This series contains the non-controversial and already
> reviewed patches (rebased) from this previous series:
> "Remove one use of qemu_get_cpu() in A7/A15 MPCore priv"
> https://lore.kernel.org/qe
(series fully reviewed)
Hi,
This series contains the non-controversial and already
reviewed patches (rebased) from this previous series:
"Remove one use of qemu_get_cpu() in A7/A15 MPCore priv"
https://lore.kernel.org/qemu-devel/20231212162935.42910-1-phi...@linaro.org/
Posted separately to avoi
CSR registers is import system control registers, it had better to dump
all CSR registers when VM is running in system mode, rather than dump
part of those, since guest OS uses these CSR registers. And it is very
useful to debug guest OS.
---
v1 .. v2:
1. Fix compiling issue on user mode onl
From: Helge Deller
This patchset adds various missing sockopt calls, so that qemu linux-user
is able to successfully build the debian gupnp package in a chroot.
Tested with a 32-bit big-endian hppa linux-user chroot running on a phyiscal
x86-64 little-endian host.
This fixes debian's bug report
Peter Xu writes:
> CI: https://gitlab.com/peterx/qemu/-/pipelines/1577280033
> (note: it's a pipeline of two patchsets, to save CI credits and time)
>
> v1: https://lore.kernel.org/r/20241204005138.702289-1-pet...@redhat.com
>
> This is v2 of the series, removing RFC tag, because my goal is to h
For a while now, I've been chasing the problem of macOS's XHCI guest driver not
working properly with QEMU's PCI XHCI controller when MSI-X is unavailable.
I've finally figured out the cause, and I think an acceptable solution. I've
explained the problem and quoted the relevant sections of the XHCI
Based-on: 20241210160452.2427965-1-peter.mayd...@linaro.org
("target/arm: Pull TLBI insns out to their own source file")
The FEAT_XS feature was introduced in ARMv8.7: it adds a new memory
attribute XS which indicates that a memory access could take longer
than usual to complete, and also adds ins
CI: https://gitlab.com/peterx/qemu/-/pipelines/1577280033
(note: it's a pipeline of two patchsets, to save CI credits and time)
v1: https://lore.kernel.org/r/20241204005138.702289-1-pet...@redhat.com
This is v2 of the series, removing RFC tag, because my goal is to have them
(or some newer versi
This series extends our documentation with new pages to help developers
onboarding on QEMU. It focuses on providing a big picture of QEMU (to a
modest extend).
As such, it was written to be simple, short, easy to understand, and pointing to
more details. It provides another way to dive into detail
change from v1:
This patch series do not support boot from an eMMC.
Only support eMMC and SD Slot 0 as storages.
change from v2:
- Add hw/sd/aspeed_sdhci: Fix coding style patch
Jamin Lin (6):
hw/sd/aspeed_sdhci: Fix coding style
hw/arm/aspeed: Fix coding style
hw:sdhci: Introduce a new "ca
On Thu, Nov 21, 2024 at 6:09 PM Akihiko Odaki wrote:
>
> On 2024/11/21 19:05, Michael Tokarev wrote:
> > 11.11.2024 09:40, Akihiko Odaki wrote:
> >> Most of this series are fixes for software RSS and hash reporting, which
> >> should have no production user.
> >>
> >> However there is one exceptio
On 2024/11/21 19:05, Michael Tokarev wrote:
11.11.2024 09:40, Akihiko Odaki wrote:
Most of this series are fixes for software RSS and hash reporting, which
should have no production user.
However there is one exception; patch "virtio-net: Fix size check in
dhclient workaround" fixes an out-of-b
11.11.2024 09:40, Akihiko Odaki wrote:
Most of this series are fixes for software RSS and hash reporting, which
should have no production user.
However there is one exception; patch "virtio-net: Fix size check in
dhclient workaround" fixes an out-of-bound access that can be triggered
for anyone
On 12/11/24 17:20, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (6):
target/mips: Introduce decode tree bindings for microMIPS ISA
target/mips: Introduce decode tree bindings for nanoMIPS ISA
target/mips: Have gen_[d]lsa() callers add 1 to shift amount argument
target/mips: D
Prepare buildsys to decode micro/nanoMIPS opcodes using
the decodetree script.
Simplify gen_lsa/dsa() and convert micro/nanoMIPS LSA
opcode to decodetree.
Philippe Mathieu-Daudé (6):
target/mips: Introduce decode tree bindings for microMIPS ISA
target/mips: Introduce decode tree bindings for n
Most of this series are fixes for software RSS and hash reporting, which
should have no production user.
However there is one exception; patch "virtio-net: Fix size check in
dhclient workaround" fixes an out-of-bound access that can be triggered
for anyone who don't use vhost. It has Cc: qemu-sta.
> ; wangyanan (Y)
> ; jiakern...@gmail.com;
> maob...@loongson.cn; lixiang...@loongson.cn; shahu...@redhat.com;
> zhao1....@intel.com; Linuxarm ;
> gustavo.rom...@linaro.org
> Subject: [PATCH V2 0/6] Arch agnostic ACPI changes to support vCPU
> Hotplug (on Archs like ARM)
Change Log
==
Patch V1 -> V2:
1. Addressed Igor Mammedov's (Redhat) raised issues:
- Removed `ACPICPUstatus::is_present` State and its handling in the
ACPI APUs AML code and now all QOM vCPUs are present.
- Dropped the concept of `acpi_persistent` because now QOM vCPUs
stat
On 10/24/24 15:45, Alex Bennée wrote:
> Dmitry Osipenko writes:
>
>> On 10/24/24 13:09, Alex Bennée wrote:
>>> Dmitry Osipenko writes:
>>>
This patchset adds DRM native context support to VirtIO-GPU on Qemu.
It's based on the pending Venus v17 patches [1] that bring host blobs
sup
Dmitry Osipenko writes:
> On 10/24/24 13:09, Alex Bennée wrote:
>> Dmitry Osipenko writes:
>>
>>> This patchset adds DRM native context support to VirtIO-GPU on Qemu.
>>> It's based on the pending Venus v17 patches [1] that bring host blobs
>>> support to virtio-gpu-gl device.
>>>
>>> Based-on:
On 10/24/24 13:09, Alex Bennée wrote:
> Dmitry Osipenko writes:
>
>> This patchset adds DRM native context support to VirtIO-GPU on Qemu.
>> It's based on the pending Venus v17 patches [1] that bring host blobs
>> support to virtio-gpu-gl device.
>>
>> Based-on: 20240822185110.1757429-1-dmitry.os
Dmitry Osipenko writes:
> This patchset adds DRM native context support to VirtIO-GPU on Qemu.
> It's based on the pending Venus v17 patches [1] that bring host blobs
> support to virtio-gpu-gl device.
>
> Based-on: 20240822185110.1757429-1-dmitry.osipe...@collabora.com
>
> [1]
> https://lore.ker
This patchset adds DRM native context support to VirtIO-GPU on Qemu.
It's based on the pending Venus v17 patches [1] that bring host blobs
support to virtio-gpu-gl device.
Based-on: 20240822185110.1757429-1-dmitry.osipe...@collabora.com
[1]
https://lore.kernel.org/qemu-devel/20240822185110.17574
On 10/3/24 07:00, Peter Maydell wrote:
This series is the remaining patches not yet applied from my "arm:
Drop deprecated boards" series; this is essentially the device
removals which didn't get review in that series and/or which had some
discussion about whether we should remove them.
To summar
This series is the remaining patches not yet applied from my "arm:
Drop deprecated boards" series; this is essentially the device
removals which didn't get review in that series and/or which had some
discussion about whether we should remove them.
To summarise the remaining removals:
* max1110 a
v1: Support GPIO for AST2700
v2: Fix clear incorrect interrupt status and adds reviewer suggestion
Jamin Lin (6):
hw/gpio/aspeed: Fix coding style
hw/gpio/aspeed: Support to set the different memory size
hw/gpio/aspeed: Support different memory region ops
hw/gpio/aspeed: Fix clear incorrec
Akihiko Odaki writes:
> Unlike GCC, clang checks if the operands in assembly matches with the
> type in C. It also does not support "x" constraint for AArch64 and
> complains about them.
I guess there are more needed:
ninja: no work to do.
/home/alex/lsrc/qemu.git/builds/all.clang/pyvenv/bi
Unlike GCC, clang checks if the operands in assembly matches with the
type in C. It also does not support "x" constraint for AArch64 and
complains about them.
Signed-off-by: Akihiko Odaki
---
Changes in v2:
- Removed spurious a compiler flag change for normal SME tests.
- Fixed sme-i16i64 detecti
Hi Paolo,
A gentle poke for this series.
Thanks,
Zhao
On Thu, Jun 06, 2024 at 05:25:31PM +0800, Zhao Liu wrote:
> Date: Thu, 6 Jun 2024 17:25:31 +0800
> From: Zhao Liu
> Subject: Re: [PATCH v2 0/6] target/i386: Misc cleanup on KVM PV defs and
> outdated comments
>
> Hi
Hi Rajnesh,
On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote:
This series enables Control Transfer Records extension support on riscv
platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here [0]
CTR extension depen
On Thu, Jun 20, 2024 at 1:28 AM Rajnesh Kanwal wrote:
>
> This series enables Control Transfer Records extension support on riscv
> platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
> The Extension has been stable and the latest release can be found here [0]
Can you be expli
This series enables Control Transfer Records extension support on riscv
platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here [0]
CTR extension depends on couple of other extensions:
1. S[m|s]csrind : The ind
From: Frank Chang
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
impl
Hi Paolo,
Just a ping for this cleanup series.
Thanks,
Zhao
On Mon, May 06, 2024 at 04:51:47PM +0800, Zhao Liu wrote:
> Date: Mon, 6 May 2024 16:51:47 +0800
> From: Zhao Liu
> Subject: [PATCH v2 0/6] target/i386: Misc cleanup on KVM PV defs and
> outdated comments
> X-Mailer:
Hi,
This RFC patch set tries to fix the issue of
https://gitlab.com/qemu-project/qemu/-/issues/2137.
In this new version, we added patches that try to load/store more data
at a time in part of vector continuous load/store (unit-stride/whole
register) instructions with some assumptions (e.g. no ma
On Fri, 31 May 2024 at 14:48, Peter Maydell wrote:
>
> On Fri, 24 May 2024 at 18:08, Don Porter wrote:
> >
> > This version of the 'info pg' command adopts Peter Maydell's request
> > to write some guest-agnostic page table iterator and accessor code,
> > along with architecture-specific hooks.
On Fri, 24 May 2024 at 18:08, Don Porter wrote:
>
> This version of the 'info pg' command adopts Peter Maydell's request
> to write some guest-agnostic page table iterator and accessor code,
> along with architecture-specific hooks. The first patch in this
> series contributes a generic page tabl
A v3 was just sent, with a fix to the algorithm used.
On 5/30/24 10:49, Pierrick Bouvier wrote:
The goal here is to be able to scale temporally execution of qemu-user/system,
using a given number of instructions per second.
We define a virtual clock, that can be late or in advance compared to r
The goal here is to be able to scale temporally execution of qemu-user/system,
using a given number of instructions per second.
We define a virtual clock, that can be late or in advance compared to real time.
When we are in advance, we slow execution (by sleeping) until catching real
time.
Finall
Hi mainatainers,
Just a friendly ping.
Thanks,
Zhao
On Mon, May 06, 2024 at 04:51:47PM +0800, Zhao Liu wrote:
> Date: Mon, 6 May 2024 16:51:47 +0800
> From: Zhao Liu
> Subject: [PATCH v2 0/6] target/i386: Misc cleanup on KVM PV defs and
> outdated comments
> X-Mailer: git-se
Since v1:
- Added "TCG" in subject since it is enabling for TCG
- Enable test_mode_reboot with checking GITLAB_CI env that Fabiano
suggested.
- Move test_ignore_shared patch out of the s390 fix series to here
and use GITLAB_CI for it too.
- Move ppc64 pseries machine options out of libqos-spapr
This version of the 'info pg' command adopts Peter Maydell's request
to write some guest-agnostic page table iterator and accessor code,
along with architecture-specific hooks. The first patch in this
series contributes a generic page table iterator and an x86
instantiation. As a client, we first
The goal of these patches is to add support to a variety of virtio and
vhost devices for the VIRTIO_F_IN_ORDER transport feature. This feature
indicates that all buffers are used by the device in the same order in
which they were made available by the driver.
These patches attempt to implement a g
在 2024/5/7 上午11:48, Bibo Mao 写道:
One LoongArch virt machine platform, there is limitation for memory
map information. The minimum memory size is 256M and minimum memory
size for numa node0 is 256M also. With qemu numa qtest, it is possible
that memory size of numa node0 is 128M.
Limitations for
Am 8. Mai 2024 14:53:49 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 30/4/24 17:06, Bernhard Beschow wrote:
>
>> Bernhard Beschow (6):
>>hw/i386/x86: Eliminate two if statements in x86_bios_rom_init()
>>hw/i386: Have x86_bios_rom_init() take X86MachineState rather than
>> MachineStat
On 30/4/24 17:06, Bernhard Beschow wrote:
Bernhard Beschow (6):
hw/i386/x86: Eliminate two if statements in x86_bios_rom_init()
hw/i386: Have x86_bios_rom_init() take X86MachineState rather than
MachineState
hw/i386/x86: Don't leak "isa-bios" memory regions
Patches 1-3 queued.
This is a follow up to the "default y" patch series at
https://lore.kernel.org/qemu-devel/20240423131612.28362-1-pbonz...@redhat.com/
and shows an example of what that series enables.
With this change, individual boards will be enabled/disabled depending
on whether libfdt is present or not. In pa
One LoongArch virt machine platform, there is limitation for memory
map information. The minimum memory size is 256M and minimum memory
size for numa node0 is 256M also. With qemu numa qtest, it is possible
that memory size of numa node0 is 128M.
Limitations for minimum memory size for both total
Hi,
This is my v2 cleanup series. Compared with v1 [1], only tags (R/b, S/b)
updates, and a typo fix, no code change.
This series picks cleanup from my previous kvmclock [2] (as other
renaming attempts were temporarily put on hold).
In addition, this series also include the cleanup on a historic
region which matches real hardware and which some real-world legacy bioses I'm
running rely on. Furthermore, aliasing in the isa-bios area is already the
current behavior in the bios (a.k.a. ROM) case, so this series consolidates
behavior.
For migration compatibility the aliasing is only performed
[respinning because master moved and there were conflicts]
Hi everyone,
Here's some cleaning up of deprecated code. It removes the old block
migration and compression code. Both have suitable replacements in the
form of the blockdev-mirror driver and multifd compression,
respectively.
There's al
Hello,
Thank You so much for reviewing patchset V1.
In PATCHSET V2, removed the PNV_SPI_RESPONDER model and an existing
QEMU SSI framework is used to model SPI BUS and SEEPROM model and
also most of Steve's comments have been addressed.
Also added the pnv-spi-seeprom qtest is added to test to che
Alison Schofield wrote:
> On Fri, Mar 29, 2024 at 11:22:32AM -0700, Dan Williams wrote:
> > Alison Schofield wrote:
> > [..]
> > > Upon receipt of that new poison list, call memory_failture_queue()
> > > on *any* poison in a mapped space. Is that OK? Can we call
> > > memory_failure_queue() on any
On Fri, Mar 29, 2024 at 11:22:32AM -0700, Dan Williams wrote:
> Alison Schofield wrote:
> [..]
> > Upon receipt of that new poison list, call memory_failture_queue()
> > on *any* poison in a mapped space. Is that OK? Can we call
> > memory_failure_queue() on any and every poison report that is in
Alison Schofield wrote:
[..]
> Upon receipt of that new poison list, call memory_failture_queue()
> on *any* poison in a mapped space. Is that OK? Can we call
> memory_failure_queue() on any and every poison report that is in
> HPA space regardless of whether it first came to us through a GMER?
>
On Fri, Mar 29, 2024 at 02:36:08PM +0800, Shiyang Ruan wrote:
> Changes:
> RFCv1 -> RFCv2:
> 1. update commit message of PATCH 1
> 2. use memory_failure_queue() instead of MCE
> 3. also report poison in debugfs when injecting poison
> 4. correct DPA->HPA logic:
> find memdev's endpoint decoder
Changes:
RFCv1 -> RFCv2:
1. update commit message of PATCH 1
2. use memory_failure_queue() instead of MCE
3. also report poison in debugfs when injecting poison
4. correct DPA->HPA logic:
find memdev's endpoint decoder to find the region it belongs to
5. distinguish transaction_type of GMER, o
On Sun, 24 Mar 2024 at 16:56, Arnaud Minier
wrote:
>
> This patch adds the STM32L4x5 USART
> (Universal Synchronous/Asynchronous Receiver/Transmitter)
> device and is part of a series implementing the
> STM32L4x5 with a few peripherals.
>
> It implements the necessary functionalities to receive/se
This patch adds the STM32L4x5 USART
(Universal Synchronous/Asynchronous Receiver/Transmitter)
device and is part of a series implementing the
STM32L4x5 with a few peripherals.
It implements the necessary functionalities to receive/send
characters over the serial port, which are useful to
communica
Hi,
here are a few fixes for the hppa target i made while debugging
some wide mode issues.
Changes in v2:
- use Richards version for access id matching
- add trans_fic()
Sven Schnelle (6):
target/hppa: ldcw,s uses static shift of 3
target/hppa: fix shrp for wide mode
target/hppa: fix acce
The goal of these patches are to add support to a variety of virtio and
vhost devices for the VIRTIO_F_NOTIFICATION_DATA transport feature. This
feature indicates that a driver will pass extra data (instead of just a
virtqueue's index) when notifying the corresponding device.
The data passed in by
v2:
- now based on master
- drop x- prefixes, still keep new APIs "unstable"
Also:
01: add a-b by Raphael
add note about removed comment "valid for resize only"
02-03: new patches, following review of old "02", which is now 04
04: use GenericError
wording
keep short name device-sync-c
On 26/2/24 18:37, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (6):
hw/arm: Inline sysbus_create_simple(PL110 / PL111)
hw/display/pl110: Pass frame buffer memory region as link property
hw/arm/exynos4210: Inline sysbus_create_varargs(EXYNOS4210_FIMD)
hw/display/exynos4210_fim
On 24/2/24 14:58, Bernhard Beschow wrote:
The series aims to simplify the initialization process of all PC-based machines
by streamlining redundant code.
Bernhard Beschow (6):
hw/i386/x86: Let ioapic_init_gsi() take parent as pointer
hw/i386/pc: Rename "bus" attribute to "pcibus"
hw/i
(all series reviewed)
Since v1:
- Rebased
Pass address space as link property for devices where
it seems to matter, otherwise just use get_system_memory().
Philippe Mathieu-Daudé (6):
hw/arm: Inline sysbus_create_simple(PL110 / PL111)
hw/display/pl110: Pass frame buffer memory region as link
Am 24. Februar 2024 13:58:45 UTC schrieb Bernhard Beschow :
>The series aims to simplify the initialization process of all PC-based machines
>
>by streamlining redundant code.
>
>
>
>Since I haven't seen patches on the list so far for folding CMOS data
>
>generation into pc.c, which frees all PC
The series aims to simplify the initialization process of all PC-based machines
by streamlining redundant code.
Since I haven't seen patches on the list so far for folding CMOS data
generation into pc.c, which frees all PC machines from performing this duty
explicitly, I've appended this cleanup a
On Sun, Feb 18, 2024 at 5:27 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This second version was rebased with current
> alistair/riscv.to.apply-next and has typo fixes in patch 1. No other
> changes were made.
>
> All patches reviewed/acked.
>
> Changes from v1:
> - patch 1: typos in the commit
Hi Phil,
On 2/16/24 11:44 AM, Philippe Mathieu-Daudé wrote:
This is a respin of Gustavo's v1 [3].
Since v1:
- Respin splitting controversial code in another patch
- For minor changes see notes in patch #1
Thanks for the respin/split!
I don't know if I should review it and you would send a v
Hi,
This second version was rebased with current
alistair/riscv.to.apply-next and has typo fixes in patch 1. No other
changes were made.
All patches reviewed/acked.
Changes from v1:
- patch 1: typos in the commit message fixed
- v1 link:
https://lore.kernel.org/qemu-riscv/20240213191736.74-
This is a respin of Gustavo's v1 [3].
Since v1:
- Respin splitting controversial code in another patch
- For minor changes see notes in patch #1
--
This patchset introduces a new device, ivshmem-flat, which is similar to the
current ivshmem device but does not require a PCI bus. It implements th
I submitted a RFC series[1] to add support for SR-IOV emulation to
virtio-net-pci. During the development of the series, I fixed some
trivial bugs and made improvements that I think are independently
useful. This series extracts those fixes and improvements from the RFC
series. Below is an explanat
On 2/7/24 00:54, Peter Maydell wrote:
On Tue, 6 Feb 2024 at 03:07, Richard Henderson
wrote:
The first patch is unchanged from
Supercedes: <20240131003557.176486-1-richard.hender...@linaro.org>
while the remaining patches replace
Supercedes: <20240205023948.25476-1-richard.hender...@linaro.o
Hi Richard,
On 2/6/24 12:05 AM, Richard Henderson wrote:
The first patch is unchanged from
Supercedes: <20240131003557.176486-1-richard.hender...@linaro.org>
while the remaining patches replace
Supercedes: <20240205023948.25476-1-richard.hender...@linaro.org>
While digging through Gustavo's
On Tue, 6 Feb 2024 at 03:07, Richard Henderson
wrote:
>
> The first patch is unchanged from
>
> Supercedes: <20240131003557.176486-1-richard.hender...@linaro.org>
>
> while the remaining patches replace
>
> Supercedes: <20240205023948.25476-1-richard.hender...@linaro.org>
>
> While digging through
On Mon, Feb 05, 2024 at 04:49:23PM -0300, Fabiano Rosas wrote:
> Based-on: 20240202102857.110210-1-pet...@redhat.com
> [PATCH v2 00/23] migration/multifd: Refactor ->send_prepare() and cleanups
> https://lore.kernel.org/r/20240202102857.110210-1-pet...@redhat.com
>
> Hi,
>
> In this v2 I made sur
The first patch is unchanged from
Supercedes: <20240131003557.176486-1-richard.hender...@linaro.org>
while the remaining patches replace
Supercedes: <20240205023948.25476-1-richard.hender...@linaro.org>
While digging through Gustavo's test case, wondering why it
should be failing at all, I fina
Based-on: 20240202102857.110210-1-pet...@redhat.com
[PATCH v2 00/23] migration/multifd: Refactor ->send_prepare() and cleanups
https://lore.kernel.org/r/20240202102857.110210-1-pet...@redhat.com
Hi,
In this v2 I made sure NO channel is created after the semaphores are
posted. Feel free to call me
Hi,
This is a bundle of fixes based on discoveries that were made in the
last week or so:
- what we call "named features" are actually real extensions, which are
considered to be ratified by the profile spec that defines them. This
means that we need to add riscv,isa strings for them. More in
Since v1:
- Add missing QOM parent for CPU cores
- Dropped Aspeed changes (Cédric)
Following Gavin recent CPU type enforcement cleanups,
restrict more single-CPU ARM machines (here Cortex-A SoC).
Based-on: <20240118200643.29037-1-phi...@linaro.org> (arm-next)
Philippe Mathieu-Daudé (6):
hw/arm
Hi,
As per Richard's suggestion I made pmm field part of tb_flags.
It allowed to get rid of global variable to store pmlen.
Also it allowed to simplify all the machinery around it.
Thanks
[v1]:
Hi all,
It looks like Zjpm v0.8 is almost frozen and we don't expect it change
drastically anymore.
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