Re: [PATCH v2 0/3] Add QEMU model for ASPEED OTP memory and integrate with SoC

2025-06-27 Thread Cédric Le Goater
On 6/27/25 11:09, Kane Chen wrote: Hi Cédric, Thanks for your reviewing and comments. Regarding the drive property and block backend, my understanding is that the following changes would be required: 1. Add a BlockBackend field in AspeedOTPState 2. Register a drive property to associate the b

RE: [PATCH v2 0/3] Add QEMU model for ASPEED OTP memory and integrate with SoC

2025-06-27 Thread Kane Chen
t; ; Steven Lee ; Troy > Lee ; Jamin Lin ; Andrew > Jeffery ; Joel Stanley ; > open list:ASPEED BMCs ; open list:All patches CC > here > Cc: Troy Lee > Subject: Re: [PATCH v2 0/3] Add QEMU model for ASPEED OTP memory and > integrate with SoC > > On 6/27/25 04:5

Re: [PATCH v2 0/3] Add QEMU model for ASPEED OTP memory and integrate with SoC

2025-06-26 Thread Cédric Le Goater
On 6/27/25 04:56, Kane Chen wrote: From: Kane-Chen-AS This patch series introduces a QEMU model for the ASPEED OTP (One-Time Programmable) memory, along with its integration into the Secure Boot Controller (SBC) and supported SoC (AST2600). The OTP model emulates a simple fuse array used for s

[PATCH v2 0/3] Add QEMU model for ASPEED OTP memory and integrate with SoC

2025-06-26 Thread Kane Chen via
From: Kane-Chen-AS This patch series introduces a QEMU model for the ASPEED OTP (One-Time Programmable) memory, along with its integration into the Secure Boot Controller (SBC) and supported SoC (AST2600). The OTP model emulates a simple fuse array used for secure boot or device configuration, i