On 11/3/22 23:25, Rui Wang wrote:
+/*
+ * LoongArch CPUs hardware flags.
+ * bit[2..0] for MMU index.
+ * bit[7..4] for CSR.EUEN.{ BTE, ASXE, SXE, FPE }.
+ */
+#define HW_FLAGS_MMU_MASK 0x07
+#define HW_FLAGS_EUEN_FPE 0x10
+
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env,
We need to emulate it to generate a floating point disable exception
when CSR.EUEN.FPE is zero.
Signed-off-by: Rui Wang
---
target/loongarch/cpu.c| 2 ++
target/loongarch/cpu.h| 13 +++
.../loongarch/insn_trans/trans_farith.c.inc | 30 ++