Re: [PATCH v2] hw/riscv: Fix OT IBEX reset vector

2021-04-21 Thread Alexander Wagner
On 21.04.21 02:00, Alistair Francis wrote: On Tue, Apr 20, 2021 at 6:01 PM Alexander Wagner wrote: The IBEX documentation [1] specifies the reset vector to be "the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte". [1] https://github.com/

Re: [PATCH v2] hw/riscv: Fix OT IBEX reset vector

2021-04-20 Thread Alistair Francis
On Tue, Apr 20, 2021 at 6:01 PM Alexander Wagner wrote: > > The IBEX documentation [1] specifies the reset vector to be "the most > significant 3 bytes of the boot address and the reset value (0x80) as > the least significant byte". > > [1] > https://github.com/lowRISC/ibex/blob/master/doc/03_ref

[PATCH v2] hw/riscv: Fix OT IBEX reset vector

2021-04-20 Thread Alexander Wagner
The IBEX documentation [1] specifies the reset vector to be "the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte". [1] https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst Signed-off-by: Alexander Wagner Revi