Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

2021-04-21 Thread Alistair Francis
On Thu, Apr 22, 2021 at 11:06 AM Richard Henderson wrote: > > On 4/19/21 6:31 PM, frank.ch...@sifive.com wrote: > > +return 3; /* deafult NaN */ > > Late notice of spelling error: default. Fixed when I applied it. Thanks! Applied to riscv-to-apply.next Alistair > > r~ >

Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

2021-04-21 Thread Richard Henderson
On 4/19/21 6:31 PM, frank.ch...@sifive.com wrote: +return 3; /* deafult NaN */ Late notice of spelling error: default. r~

Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

2021-04-21 Thread Alistair Francis
On Wed, Apr 21, 2021 at 12:17 AM Richard Henderson wrote: > > On 4/19/21 6:31 PM, frank.ch...@sifive.com wrote: > > From: Frank Chang > > > > In IEEE 754-2008 spec: > >Invalid operation exception is signaled when doing: > >fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) > >u

Re: [PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

2021-04-20 Thread Richard Henderson
On 4/19/21 6:31 PM, frank.ch...@sifive.com wrote: From: Frank Chang In IEEE 754-2008 spec: Invalid operation exception is signaled when doing: fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) unless c is a quiet NaN; if c is a quiet NaN then it is implementation defined whe

[PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

2021-04-19 Thread frank . chang
From: Frank Chang In IEEE 754-2008 spec: Invalid operation exception is signaled when doing: fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) unless c is a quiet NaN; if c is a quiet NaN then it is implementation defined whether the invalid operation exception is signaled. In