Re: [PATCH v12 3/6] target/riscv: Handle Smrnmi interrupt and exception

On Mon, Jan 6, 2025 at 3:47 PM wrote: > > From: Tommy Wu > > Because the RNMI interrupt trap handler address is implementation defined. > We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property > of the harts. It’s very easy for users to set the address based on their > exp

[PATCH v12 3/6] target/riscv: Handle Smrnmi interrupt and exception

From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to