Re: [PATCH v11 3/6] target/riscv: Handle Smrnmi interrupt and exception

2025-01-05 Thread Frank Chang
On Mon, Jan 6, 2025 at 9:45 AM Alistair Francis wrote: > On Tue, Dec 31, 2024 at 1:28 PM wrote: > > > > From: Tommy Wu > > > > Because the RNMI interrupt trap handler address is implementation > defined. > > We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the > property > > of

Re: [PATCH v11 3/6] target/riscv: Handle Smrnmi interrupt and exception

2025-01-05 Thread Alistair Francis
On Tue, Dec 31, 2024 at 1:28 PM wrote: > > From: Tommy Wu > > Because the RNMI interrupt trap handler address is implementation defined. > We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property > of the harts. It’s very easy for users to set the address based on their > ex

[PATCH v11 3/6] target/riscv: Handle Smrnmi interrupt and exception

2024-12-30 Thread frank . chang
From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to