Re: [PATCH v10 3/7] target/riscv: Handle Smrnmi interrupt and exception

On 12/31/24 12:11 AM, Frank Chang wrote: On Thu, Dec 26, 2024 at 8:42 PM Daniel Henrique Barboza mailto:dbarb...@ventanamicro.com>> wrote: On 12/17/24 3:24 AM, frank.ch...@sifive.com wrote: > From: Tommy Wu mailto:tommy...@sifive.com>> > >

Re: [PATCH v10 3/7] target/riscv: Handle Smrnmi interrupt and exception

On Thu, Dec 26, 2024 at 8:42 PM Daniel Henrique Barboza < dbarb...@ventanamicro.com> wrote: > > > On 12/17/24 3:24 AM, frank.ch...@sifive.com wrote: > > From: Tommy Wu > > > > Because the RNMI interrupt trap handler address is implementation > defined. > > We add the 'rnmi-interrupt-vector' and '

Re: [PATCH v10 3/7] target/riscv: Handle Smrnmi interrupt and exception

On 12/17/24 3:24 AM, frank.ch...@sifive.com wrote: From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their

[PATCH v10 3/7] target/riscv: Handle Smrnmi interrupt and exception

From: Tommy Wu Because the RNMI interrupt trap handler address is implementation defined. We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property of the harts. It’s very easy for users to set the address based on their expectation. This patch also adds the functionality to