Re: [PATCH v10 3/5] target/riscv: generate virtual instruction exception

On 2022/10/3 19:47, Mayuresh Chitale wrote: This patch adds a mechanism to generate a virtual instruction instruction exception instead of an illegal instruction exception during instruction decode when virt is enabled. Signed-off-by: Mayuresh Chitale --- target/riscv/translate.c | 9 ++

[PATCH v10 3/5] target/riscv: generate virtual instruction exception

This patch adds a mechanism to generate a virtual instruction instruction exception instead of an illegal instruction exception during instruction decode when virt is enabled. Signed-off-by: Mayuresh Chitale --- target/riscv/translate.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(