Re: [PATCH v10 1/3] hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel()

On Sat, Feb 4, 2023 at 7:01 AM Daniel Henrique Barboza wrote: > > Hey, > > On 2/3/23 07:45, Bin Meng wrote: > > Hi Daniel, > > > > On Fri, Feb 3, 2023 at 6:31 PM Daniel Henrique Barboza > > wrote: > >> > >> > >> > >> On 2/3/23 02:39, Bin Meng wrote: > >>> On Thu, Feb 2, 2023 at 9:58 PM Daniel Hen

Re: [PATCH v10 1/3] hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel()

Hey, On 2/3/23 07:45, Bin Meng wrote: Hi Daniel, On Fri, Feb 3, 2023 at 6:31 PM Daniel Henrique Barboza wrote: On 2/3/23 02:39, Bin Meng wrote: On Thu, Feb 2, 2023 at 9:58 PM Daniel Henrique Barboza wrote: load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit QEMU guest hap

Re: [PATCH v10 1/3] hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel()

Hi Daniel, On Fri, Feb 3, 2023 at 6:31 PM Daniel Henrique Barboza wrote: > > > > On 2/3/23 02:39, Bin Meng wrote: > > On Thu, Feb 2, 2023 at 9:58 PM Daniel Henrique Barboza > > wrote: > >> > >> load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit QEMU > >> guest happens to be runnin

Re: [PATCH v10 1/3] hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel()

On 2/3/23 02:39, Bin Meng wrote: On Thu, Feb 2, 2023 at 9:58 PM Daniel Henrique Barboza wrote: load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit QEMU guest happens to be running in a hypervisor that are using 64 bits to encode its address, kernel_entry can be padded with '1'

Re: [PATCH v10 1/3] hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel()

On Thu, Feb 2, 2023 at 9:58 PM Daniel Henrique Barboza wrote: > > load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit QEMU > guest happens to be running in a hypervisor that are using 64 bits to > encode its address, kernel_entry can be padded with '1's and create > problems [1]. St

Re: [PATCH v10 1/3] hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel()

On Thu, Feb 2, 2023 at 11:58 PM Daniel Henrique Barboza wrote: > > load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit QEMU > guest happens to be running in a hypervisor that are using 64 bits to > encode its address, kernel_entry can be padded with '1's and create > problems [1]. >

[PATCH v10 1/3] hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel()

load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit QEMU guest happens to be running in a hypervisor that are using 64 bits to encode its address, kernel_entry can be padded with '1's and create problems [1]. Using a translate_fn() callback in load_elf_ram_sym() to filter the padding

[PATCH v10 1/3] hw/riscv: handle 32 bit CPUs kernel_addr in riscv_load_kernel()

load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit QEMU guest happens to be running in a hypervisor that are using 64 bits to encode its address, kernel_entry can be padded with '1's and create problems [1]. Using a translate_fn() callback in load_elf_ram_sym() to filter the padding