particular memory contents (was:
> [PATCH v1 0/1] hw/misc/aspeed_sbc: Implement OTP memory and controller)
>
> Cédric Le Goater writes:
>
> > Hello Kane,
> >
> > + Markus (for ebc29e1beab0 implementation)
> >
> > On 4/7/25 09:33, Kane Chen wrote:
>
ere
> ; qemu-block ; Markus
> Armbruster
> Cc: Troy Lee
> Subject: Re: [PATCH v1 0/1] hw/misc/aspeed_sbc: Implement OTP memory and
> controller
>
> Hello Kane,
>
> + Markus (for ebc29e1beab0 implementation)
>
> On 4/7/25 09:33, Kane Chen wrote:
> > Hi Cédric/Phi
Cédric Le Goater writes:
> Hello Kane,
>
> + Markus (for ebc29e1beab0 implementation)
>
> On 4/7/25 09:33, Kane Chen wrote:
>> Hi Cédric/Philippe,
>> OTP (One-Time Programmable) memory is a type of non-volatile memory
>> in which each bit can be programmed only once. It is typically used
>> to st
e Mathieu-Daudé ; Kane Chen
; Peter Maydell ;
Steven Lee ; Troy Lee ;
Jamin Lin ; Andrew Jeffery
; Joel Stanley ; open
list:ASPEED BMCs ; open list:All patches CC here
; qemu-block
Cc: Troy Lee
Subject: Re: [PATCH v1 0/1] hw/misc/aspeed_sbc: Implement OTP memory and
controller
On 4/4/25 15:00, P
ASPEED BMCs ; open list:All patches CC here
> ; qemu-block
> Cc: Troy Lee
> Subject: Re: [PATCH v1 0/1] hw/misc/aspeed_sbc: Implement OTP memory and
> controller
>
> On 4/4/25 15:00, Philippe Mathieu-Daudé wrote:
> > +qemu-block@
> >
> > On 4/4/25 14:06, Cédric Le Go
On 4/4/25 15:00, Philippe Mathieu-Daudé wrote:
+qemu-block@
On 4/4/25 14:06, Cédric Le Goater wrote:
Hello,
On 4/2/25 11:14, Kane-Chen-AS wrote:
This patch introduces part of the Secure Boot Controller device,
which consists of several sub-components, including an OTP memory,
OTP controller,
+qemu-block@
On 4/4/25 14:06, Cédric Le Goater wrote:
Hello,
On 4/2/25 11:14, Kane-Chen-AS wrote:
This patch introduces part of the Secure Boot Controller device,
which consists of several sub-components, including an OTP memory,
OTP controller, cryptographic engine, and boot controller.
In t
Hello,
On 4/2/25 11:14, Kane-Chen-AS wrote:
This patch introduces part of the Secure Boot Controller device,
which consists of several sub-components, including an OTP memory,
OTP controller, cryptographic engine, and boot controller.
In this version, the implementation includes the OTP memory
This patch introduces part of the Secure Boot Controller device,
which consists of several sub-components, including an OTP memory,
OTP controller, cryptographic engine, and boot controller.
In this version, the implementation includes the OTP memory and its
controller. The OTP memory can be progr
