Re: [PATCH qemu] target/riscv: Add Zilsd and Zcmlsd extension support

On 7/2/24 01:10, ~liuxu wrote: +static bool gen_load_ld(DisasContext *ctx, arg_lb *a, MemOp memop, int flag) +{ +REQUIRE_ZCMLSD(ctx); +REQUIRE_32BIT(ctx); + +if (flag&&a->rd==0){ +return false; +} + +TCGv dest_low= dest_gpr(ctx, a->rd); +TCGv addr = get_address(ctx

Re: [PATCH qemu] target/riscv: Add Zilsd and Zcmlsd extension support

On Wed, Jul 3, 2024 at 1:29 PM ~liuxu wrote: > > From: lxx <1733205...@qq.com> > > This patch adds support for the Zilsd and Zcmlsd extension, > which is documented at > https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0 > > Co-developed-by: SUN Dongya > Co-developed-by: LIU Xu > Co-devel

[PATCH qemu] target/riscv: Add Zilsd and Zcmlsd extension support

From: lxx <1733205...@qq.com> This patch adds support for the Zilsd and Zcmlsd extension, which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0 Co-developed-by: SUN Dongya Co-developed-by: LIU Xu Co-developed-by: ZHAO Fujin --- target/riscv/cpu.c