Re: [PATCH for-9.1 v3 1/2] target/riscv/debug: set tval=pc in breakpoint exceptions

On Wed, Apr 17, 2024 at 9:05 AM Daniel Henrique Barboza wrote: > > We're not setting (s/m)tval when triggering breakpoints of type 2 > (mcontrol) and 6 (mcontrol6). According to the debug spec section > 5.7.12, "Match Control Type 6": > > "The Privileged Spec says that breakpoint exceptions that o

Re: [PATCH for-9.1 v3 1/2] target/riscv/debug: set tval=pc in breakpoint exceptions

On 2024/4/17 7:04, Daniel Henrique Barboza wrote: We're not setting (s/m)tval when triggering breakpoints of type 2 (mcontrol) and 6 (mcontrol6). According to the debug spec section 5.7.12, "Match Control Type 6": "The Privileged Spec says that breakpoint exceptions that occur on instruction f

[PATCH for-9.1 v3 1/2] target/riscv/debug: set tval=pc in breakpoint exceptions

We're not setting (s/m)tval when triggering breakpoints of type 2 (mcontrol) and 6 (mcontrol6). According to the debug spec section 5.7.12, "Match Control Type 6": "The Privileged Spec says that breakpoint exceptions that occur on instruction fetches, loads, or stores update the tval CSR with eith