Re: [PATCH for-9.0] target/riscv/debug: set tval=pc in breakpoint exceptions

2024-04-10 Thread Daniel Henrique Barboza
On 3/22/24 00:59, Alistair Francis wrote: On Wed, Mar 20, 2024 at 7:33 PM Daniel Henrique Barboza wrote: We're not setting (s/m)tval when triggering breakpoints of type 2 (mcontrol) and 6 (mcontrol6). According to the debug spec section 5.7.12, "Match Control Type 6": "The Privileged Spec

Re: [PATCH for-9.0] target/riscv/debug: set tval=pc in breakpoint exceptions

2024-03-21 Thread Alistair Francis
On Wed, Mar 20, 2024 at 7:33 PM Daniel Henrique Barboza wrote: > > We're not setting (s/m)tval when triggering breakpoints of type 2 > (mcontrol) and 6 (mcontrol6). According to the debug spec section > 5.7.12, "Match Control Type 6": > > "The Privileged Spec says that breakpoint exceptions that o

[PATCH for-9.0] target/riscv/debug: set tval=pc in breakpoint exceptions

2024-03-20 Thread Daniel Henrique Barboza
We're not setting (s/m)tval when triggering breakpoints of type 2 (mcontrol) and 6 (mcontrol6). According to the debug spec section 5.7.12, "Match Control Type 6": "The Privileged Spec says that breakpoint exceptions that occur on instruction fetches, loads, or stores update the tval CSR with eith