On Thu, 6 Aug 2020 at 13:38, Philippe Mathieu-Daudé wrote:
> > @@ -206,6 +206,19 @@ static void aspeed_sdmc_reset(DeviceState *dev)
> >
> > /* Set ram size bit and defaults values */
> > s->regs[R_CONF] = asc->compute_conf(s, 0);
> > +
> > +/*
> > + * PHY status:
> > + * -
On 8/6/20 3:21 PM, Cédric Le Goater wrote:
> From: Joel Stanley
>
> This allows qemu to run the "normal" power on reset boot path through
> u-boot, where the DDR is trained.
>
> An enhancement would be to have the SCU bit stick across qemu reboots,
> but be unset on initial boot.
>
> Proper mod
From: Joel Stanley
This allows qemu to run the "normal" power on reset boot path through
u-boot, where the DDR is trained.
An enhancement would be to have the SCU bit stick across qemu reboots,
but be unset on initial boot.
Proper modelling would be to discard all writes to the phy setting regs
