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> > Cc: pal...@dabbelt.com; alistair.fran...@wdc.com;
> > sag...@eecs.berkeley.edu; kbast...@mail.uni-paderborn.de; Zhangxiaofeng
> > (F) ; Wubin (H) ;
> > Zhanghailiang ; dengkai (A)
> > ; yinyipeng
> > Subject: Re: [PATCH V3] target/riscv: raise exce
s.berkeley.edu; kbast...@mail.uni-paderborn.de; Zhangxiaofeng
> (F) ; Wubin (H) ;
> Zhanghailiang ; dengkai (A)
> ; yinyipeng
> Subject: Re: [PATCH V3] target/riscv: raise exception to HS-mode at
> get_physical_address
>
> On 10/14/20 3:17 AM, Yifei Jiang wrot
On 10/14/20 3:17 AM, Yifei Jiang wrote:
> +if (fault_pte_addr) {
> +*fault_pte_addr = (base + idx * ptesize) >> 2;
The shift is wrong. It should be exactly like...
> +}
> +return TRANSLATE_G_STAGE_FAIL;
> }
>
>
On Wed, Oct 14, 2020 at 3:18 AM Yifei Jiang wrote:
>
> VS-stage translation at get_physical_address needs to translate pte
> address by G-stage translation. But the G-stage translation error
> can not be distinguished from VS-stage translation error in
> riscv_cpu_tlb_fill. On migration, destinati
VS-stage translation at get_physical_address needs to translate pte
address by G-stage translation. But the G-stage translation error
can not be distinguished from VS-stage translation error in
riscv_cpu_tlb_fill. On migration, destination needs to rebuild pte,
and this G-stage translation error mu
