RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

2020-10-14 Thread Jiangyifei
mail.uni-paderborn.de; Zhangxiaofeng > (F) ; alistair.fran...@wdc.com; yinyipeng > ; pal...@dabbelt.com; Wubin (H) > ; dengkai (A) > Subject: Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU > > On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson > wrote: >

Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

2020-10-14 Thread Alistair Francis
On Wed, Oct 14, 2020 at 8:45 AM Richard Henderson wrote: > > On 10/14/20 3:21 AM, Jiangyifei wrote: > >> Would this be a good time to expand mstatus to uint64_t instead of > >> target_ulong so that it can be saved as one unit and reduce some ifdefs in > >> the > >> code base? > >> > >> Similarly

Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

2020-10-14 Thread Richard Henderson
On 10/14/20 3:21 AM, Jiangyifei wrote: >> Would this be a good time to expand mstatus to uint64_t instead of >> target_ulong so that it can be saved as one unit and reduce some ifdefs in >> the >> code base? >> >> Similarly with some of the other status registers that are two halved for >> riscv32

RE: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

2020-10-14 Thread Jiangyifei
s.berkeley.edu; kbast...@mail.uni-paderborn.de; Zhangxiaofeng > (F) ; Wubin (H) ; > Zhanghailiang ; dengkai (A) > ; yinyipeng > Subject: Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU > > On 10/10/20 3:06 AM, Yifei Jiang wrote: > > +++ b/target/riscv/cpu

Re: [PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

2020-10-10 Thread Richard Henderson
On 10/10/20 3:06 AM, Yifei Jiang wrote: > +++ b/target/riscv/cpu.h > @@ -311,6 +311,10 @@ extern const char * const riscv_fpr_regnames[]; > extern const char * const riscv_excp_names[]; > extern const char * const riscv_intr_names[]; > > +#ifndef CONFIG_USER_ONLY > +extern const VMStateDescript

[PATCH V2 1/5] target/riscv: Add basic vmstate description of CPU

2020-10-10 Thread Yifei Jiang
Add basic CPU state description to the newly created machine.c Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 7 target/riscv/cpu.h | 4 +++ target/riscv/machine.c | 77 target/riscv/meson.build | 3 +-