Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler

On 2023/6/12 18:04, Christoph Müllner wrote: On Mon, Jun 12, 2023 at 12:01 PM LIU Zhiwei wrote: On 2023/6/12 17:47, Christoph Müllner wrote: On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei wrote: On 2023/5/30 21:18, Christoph Muellner wrote: From: Christoph Müllner The disassembler needs th

Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler

On Mon, Jun 12, 2023 at 12:01 PM LIU Zhiwei wrote: > > > On 2023/6/12 17:47, Christoph Müllner wrote: > > On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei wrote: > >> > >> On 2023/5/30 21:18, Christoph Muellner wrote: > >>> From: Christoph Müllner > >>> > >>> The disassembler needs the available exten

Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler

On 2023/6/12 17:47, Christoph Müllner wrote: On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei wrote: On 2023/5/30 21:18, Christoph Muellner wrote: From: Christoph Müllner The disassembler needs the available extensions in order to properly decode instructions in case of overlapping encodings (e

Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler

On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei wrote: > > > On 2023/5/30 21:18, Christoph Muellner wrote: > > From: Christoph Müllner > > > > The disassembler needs the available extensions in order > > to properly decode instructions in case of overlapping > > encodings (e.g. for vendor extensions).

Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler

On 2023/5/30 21:18, Christoph Muellner wrote: From: Christoph Müllner The disassembler needs the available extensions in order to properly decode instructions in case of overlapping encodings (e.g. for vendor extensions). Let's use the field 'disassemble_info::private_data' to store our RISC

Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler

On Tue, May 30, 2023 at 11:20 PM Christoph Muellner wrote: > > From: Christoph Müllner > > The disassembler needs the available extensions in order > to properly decode instructions in case of overlapping > encodings (e.g. for vendor extensions). > > Let's use the field 'disassemble_info::private

[PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler

From: Christoph Müllner The disassembler needs the available extensions in order to properly decode instructions in case of overlapping encodings (e.g. for vendor extensions). Let's use the field 'disassemble_info::private_data' to store our RISCVCPUConfig pointer. Signed-off-by: Christoph Müll