On 4/11/22 11:30, Richard Henderson wrote:
cpu->isar.dbgdidr
"If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and
deprecated."
Which we already handle in define_debug_regs by not defining DBGDIDR if this
value is 0.
r~
On 4/11/22 11:09, Peter Maydell wrote:
+cpu->isar.id_aa64pfr0 = 0x11001012ull;
This has the GIC field clear. On the one hand this is true
also of all our other CPU implementations. On the other hand
if we wire up a GICv3 in the board code then we will be
presenting the GIC CPU inte
On Sun, 10 Apr 2022 at 07:13, Richard Henderson
wrote:
>
> Enable the a76 for virt and sbsa board use.
>
> Signed-off-by: Richard Henderson
> ---
> hw/arm/sbsa-ref.c | 1 +
> hw/arm/virt.c | 1 +
> target/arm/cpu64.c | 64 ++
> 3 files changed,
Enable the a76 for virt and sbsa board use.
Signed-off-by: Richard Henderson
---
hw/arm/sbsa-ref.c | 1 +
hw/arm/virt.c | 1 +
target/arm/cpu64.c | 64 ++
3 files changed, 66 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
ind
